The invention relates generally to magnetic random access memory (MRAM). More particularly, the invention relates to MRAM having a shared global word line.
MRAM devices generally include an array of memory cells. The memory cells are typically configured in rows and columns. Each row generally includes a corresponding word line, and each column generally includes a corresponding bit line. FIG. 1 shows an MRAM array of memory cells 110, 120, 130, 140, and corresponding word lines (WL) and bit lines (BL). The MRAM memory cells 110, 120, 130, 140 are located at cross points of the word lines and the bit lines, and each MRAM memory cells 110, 120, 130, 140 stores a bit of information though an orientation of magnetization within the memory cells.
FIG. 2 shows an MRAM memory cell 205 in greater detail. The MRAM memory cell 205 generally includes a soft magnetic region 210, a dielectric region 220 and a hard magnetic region 230. The orientation of magnetization within the soft magnetic region 210 is non-fixed, and can assume two stable orientations as shown by the arrow M1. The hard magnetic region 230 (also referred to as a pinned magnetic region) has a fixed magnetic orientation as depicted by the arrow M2. The dielectric region 220 generally provides electrical insulation between the soft magnetic region 210 and the hard magnetic region 230.
As previously stated, the orientation of magnetization of the soft magnetic region 210 can assume two stable orientations. These two orientations which are either parallel or anti-parallel to the magnetic orientation of the hard magnetic region 230, determine the logical state of the MRAM memory cell 205.
The orientation of magnetization of the soft magnetic region 210 is determined in response to electrical currents applied to the bit lines (BL) and the word lines (WL) during a write operation to the MRAM memory cell. The electrical currents applied to the bit lines and the word lines set the orientation of the magnetization depending upon the direction of the currents flowing through the bit lines and the word lines, and therefore, the directions of the induced magnetic fields created by the currents flowing through the bit lines and the word lines.
FIG. 2A shows the orientations of the magnetization of an MRAM memory cell in greater detail. A first MRAM memory cell orientation 240 includes the magnetic orientations of both the soft magnetic region and the hard magnetic region being in the same direction. A second MRAM memory cell orientation 250 includes the magnetic orientation of the soft magnetic region and the hard magnetic region being in opposite directions. A property of MRAM memory cells is that a resistance across the MRAM memory cell is low if the magnetic orientations are the same in the two regions as for the first MRAM memory cell orientation 240. However, the resistance across the MRAM memory cell is high if the magnetic orientations are the opposite in the two regions as for the second MRAM memory cell orientation 250.
The magnetic orientations of the MRAM memory cells are set (written to) by controlling electrical currents flowing through the word lines and the bit lines, and therefore, the corresponding magnetic fields induced by the electrical currents. Because the word line and the bit line operate in combination to switch the orientation of magnetization of the selected memory cell (that is, to write to the memory cell), the word line and the bit line can be collectively referred to as write lines. Additionally, the write lines can also be used to read the logic value stored in the memory cells.
The MRAM memory cells are read by sensing a resistance across the MRAM memory cells. The resistance sensing is accomplished through the word lines and the bit lines.
Generally, a voltage potential of the word lines and bit lines is limited because the word lines and bit lines are physically connected to the MRAM memory cells. That is, a voltage potential across the MRAM memory cells of a great enough value will destroy the MRAM memory cells. Therefore, the voltage potential (and resulting current) across the word lines and bit lines must be limited to a value that does not destroy the MRAM memory cells. This limits the current flowing (and the intensity of the resulting magnetic fields) through the word lines and bit lines.
Connecting a large number of MRAM memory cells to the same word lines and bit lines can reduces the effectiveness of sensing the resistive state of a single MRAM memory cell. The MRAM memory cells are connected in parallel. Therefore, the resulting output resistance sensed between the word lines and bit lines can become small. This makes detection of the resistance of any particular MRAM memory cell more difficult.
The magnitudes of the write currents through the word lines and bit lines of prior art MRAM memory cell arrays are limited by the resistance of the word lines and the bit lines. As integrated circuits and associated MRAM memory cell array become smaller, the physical dimensions of the associated word lines and bit lines become smaller. However, the smaller the physical dimensions of the word lines and the bit lines, the greater the resistance of the word lines and the bit lines. Therefore, as the dimension of the word lines and the bit lines is reduced, the magnitudes of the write currents that can be applied to the word lines and the bit lines are reduced. The net result that the magnitude of the magnetic fields generated by the word lines and the bit lines becomes more limited as the physical size of the MRAM memory cell arrays becomes smaller.
It is desirable to have an apparatus and method that provides writing to, and reading from, MRAM memory cells. It is desirable that a voltage potential applied to word lines that set magnetization direction with the MRAM memory cell not be limited. Additionally, it is desirable to shorten word or bit lines used to sense the resistance across the MRAM memory cell. It is also desirable to minimize the processing steps required to fabricate the MRAM memory cell arrays.
The invention includes an apparatus and a method for writing to MRAM memory cells through the use a shared global word line. Voltage potentials applied to the shared global word line are not limited by characteristics of the MRAM memory cells. The apparatus and method provides for shortened sense lines, which improves the sensing of a resistive state of the MRAM memory celland A shared global word line structure according to the invention add a minimal number of processing steps to the fabrication of MRAM memory arrays.
A first embodiment of the invention includes a shared global word line MRAM structure. The MRAM structure includes a first bit line conductor oriented in a first direction. A first sense line conductor is oriented in a second direction. A first memory cell is physically connected between the first bit line conductor and the first sense line conductor. A global word line is oriented in substantially the second direction, and magnetically coupled to the first memory cell. A second bit line conductor is oriented in substantially the first direction. A second sense line conductor is oriented in substantially the second direction. A second memory cell is physically connected between the second bit line conductor and the second sense line conductor. The global word line is also magnetically coupled to the second memory cell.
The first memory cell and the second memory cell can be MRAM devices. A logical state of the MRAM devices can be determined by an orientation of magnetization of the MRAM devices. The orientation of magnetization of the first memory cell can be determined by current conducted by the first bit line and the global word line. The orientation of magnetization of the second memory cell can be determined by current conducted by the second bit line and the global word line.
A logical state of the first memory cell can be sensed by the first bit line and the first sense line. The logical state of the first memory cell can be determined by a sensing a resistance between the first bit line and the first sense line. A logical state of the second memory cell can be sensed by the second bit line and the second sense line. The logical state of the second memory cell can be determined by a sensing a resistance between the second bit line and the second sense line.
A second embodiment is similar to the first embodiment. The second embodiment includes the first bit line, the first sense line conductor and the first memory cell being a mirror image about the global word line of the second bit line, the second sense line conductor and the second memory cell.
A third embodiment is similar to the first embodiment. For the third embodiment, the global word line includes a conductive center and magnetic metal liner. The global word line providing a bi-directional magnetic field when conducting current, thereby allowing the global word line to orient magnetic states of both the first memory cell and the second memory cell.
A fourth embodiment includes method of forming a shared global word line MRAM structure. The method includes etching a trench is an oxide layer formed over a substrate. A first liner material is deposited over the trench. The deposited first liner material is ansotropically etched leaving the first liner material on edges of the trench. A magnetic metal liner material is deposited over the first liner material and the substrate. The deposited magnetic metal liner material is ansotropically etched leaving the magnetic metal liner material over the first liner material on edges of the trench. A conductive layer is deposited over the magnetic liner material and the substrate. The conductive layer is chemically, mechanically polished yielding the shared global word line.